1. Field of the Invention
The present invention relates to method and apparatus for increasing integrated circuit density. In particular, the present invention relates to a method and apparatus for semiconductor package volume and height reduction with enhanced reliability and simplification of the fabrication process for stacked semiconductor dice,
2. State of the Art
Chip-On-Board (xe2x80x9cCOBxe2x80x9d) or Board-On-Chip (xe2x80x9cBOCxe2x80x9d) technology is used to attach a semiconductor die to a carrier substrate such as a printed circuit board (xe2x80x9cPCBxe2x80x9d) and may be effected using flip-chip attachment, wire bonding, and tape automated bonding (xe2x80x9cTABxe2x80x9d).
Flip-chip attachment generally consists of electrically and mechanically attaching a semiconductor die by its active surface to a carrier substrate using a pattern of discrete conductive elements therebetween. The conductive elements are generally disposed on the active surface of the die during fabrication, but may instead be disposed on the carrier substrate. The discrete conductive elements may comprise minute conductive bumps, balls or columns of various configurations. Each conductive element is placed corresponding to superimposed, mutually aligned locations of bond pads (or other I/O locations) on the semiconductor die and terminals on the carrier substrate. The semiconductor die is thus electrically and mechanically connected to the carrier substrate by, for example, reflowing conductive bumps of solder or curing conductive or conductor-filled epoxy bumps. A dielectric underfill may then be disposed between the die and the carrier substrate for environmental protection and to enhance the mechanical attachment of the die to the carrier substrate.
Wire bonding and TAB attachment techniques generally begin with attaching a semiconductor die by its back side to the surface of a carrier substrate with an appropriate adhesive, such as an epoxy or silver solder. A plurality of fine wires are discretely attached to bond pads on the semiconductor die and then extended and bonded to corresponding terminals pad on a carrier substrate. The bond wires are generally attached through one of three conventional wire bonding techniques: ultrasonic bonding-using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding-using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding-using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. A dielectric encapsulant such as a silicone or epoxy may then be applied to protect the fine wires and bond sites. In TAB, ends of metal leads carried on an insulating tape such as a polyimide to are attached to the bond pads on the semiconductor die and corresponding terminal pads on the carrier substrate.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the number of components used to fabricate them tends to decrease due to advances in technology even though the functionality of the products increase. For example, on the average, there is approximately a 10 percent decrease in components for every product generation over the previous generation having equivalent functionality.
In integrated circuit packaging, in addition to component reduction, surface mount technology has demonstrated an increase in semiconductor chip density on a single substrate or board, resulting from more compact designs and form factors and a significant increase in integrated circuit density. However, greater integrated density is becoming significantly limited by the space or xe2x80x9creal estatexe2x80x9d available for the mounting of semiconductor dice on a carrier substrate.
One method of increasing integrated circuit density is to stack die vertically. U.S. Pat. No. 5,012,323 (xe2x80x9cthe ""323 patentxe2x80x9d) issued Apr. 30, 1991 to Farnworth teaches combining a pair of die mounted on opposing sides of a lead frame. An upper, smaller die is back-bonded to the upper surfaces of the leads of the lead frame via a first adhesively coated, insulated film layer. A lower, larger die is face-bonded to the lower surface of the lead frame at a die-bonding region via a second, adhesively coated, insulative, film layer. The wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum bond wires. The lower die must be slightly larger than the upper die in order for the die pads to be accessible from above through a bonding window in the lead frame such that wire connections can be made to the lead extensions. This arrangement has a major disadvantage from a production standpoint, due to the requirement for different-sized dice, a somewhat complex lead frame configuration and a somewhat difficult to execute wire bonding protocol.
U.S. Pat. No. 5,291,061 issued Mar. 1, 1994 to Ball teaches a multiple stacked die device containing up to four stacked die supported on a die-attach paddle of a lead frame, the assembly purportedly not exceeding the height of then-current single die packages, and wherein the bond pads of each die are wire bonded to lead fingers. The relatively low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wire bonding operation and disposition of adhesive layers between the stacked die. However, Ball requires relatively long bond wires to electrically connect the stacked dice to the lead frame. These long bond wires increase resistance and may facilitate shorting due to bond wire sweep during encapsulation. Also, Ball requires the use of spacers between the dice.
U.S. Pat. No. 5,323,060 issued Jun. 21, 1994 to Fogal et al. teaches a multi-chip module that contains stacked die devices, the terminals or bond pads of which are wire bonded to a substrate or to adjacent die devices. However, as discussed with Ball, Fogal requires long bond wires to electrically connect the stacked die bond pads to the substrate. Fogal also requires the use of spacers between the dice.
U.S. Pat. Nos. 5,422,435 and 5,495,398 to Takiar et al. (xe2x80x9cTakiarxe2x80x9d) teach stacked dice having bond wires extending to each other and to the leads of a carrier member such as a lead frame. However, Takiar also has the problem of long bond wires, as well as requiring specific sized or custom designed dice to achieve a properly stacked combination.
U.S. Pat. No. 5,973,403 issued Oct. 26, 1999 to Wark teaches stacked dice on a PCB. A first die is flip-chip mounted on the PCB and a second die is backside bonded on the first die having bond wires extending from the second die to the PCB. However, Wark also has the problem of long bond wires and the excessive and somewhat complex processing steps of both underfilling the first flip-chip mounted die and encapsulating the second die connected with bond wires.
U.S. Pat. No. 6,051,878 issued Apr. 18, 2000 to Akram et al. (xe2x80x9cAkramxe2x80x9d) teaches multiple stacked substrates having dice mounted to the substrates using both wire bonding and flip-chip techniques, where some dice are mounted on opposing substrate surfaces.
Therefore, it would be advantageous to develop a fairly straightforward technique and resulting semiconductor device assembly for increasing integrated circuit density of vertically stacked semiconductor dice by reducing the number process steps for fabricating the assembly in combination while reducing assembly height and employing commercially-available, widely-practiced semiconductor device fabrication techniques.
The present invention relates to a method and apparatus for increasing integrated circuit density by reducing package height and reducing the number of process steps for fabricating a semiconductor die assembly. The present invention includes a method and apparatus for reducing the height of a plurality of vertically stacked interposer substrates, each interposer substrate having at least one semiconductor die mounted thereon. The present invention includes stacking interposer substrates having dice mounted thereto, each die being electrically connected to conductive traces of its associated interposer substrate by wire bonding.
The present invention includes at least two oppositely-facing interposer substrates, each of the interposer substrates having secured thereto by its active surface at least one semiconductor die with a portion of its active surface and bond pads thereof exposed through an opening in the interposer substrate and wire bonds extending from the bond pads and looped through the opening to conductive terminals of a first set adjacent the opening and on the opposite side of the interposer substrate from the semiconductor die. The opposing interposer substrates are mutually electrically connected on their terminal sides by a plurality of conductive elements which extend transversely therebetween and electrically connect terminals of a second set on each interposer substrate and laterally offset from the first terminal set, conductive traces extending between associated terminals of the two sets on the same interposer substrate. A third terminal set on a die side of one of the interposer substrates carries a like second plurality of conductive elements extending transversely from that interposer substrate for electrically connecting the stacked interposer substrates to a carrier substrate. An assembly including a carrier substrate is also encompassed by the invention.
According to one embodiment of the present invention, an exposed portion of the active surface of at least one semiconductor die attached to an interposer substrate substantially directly faces and is substantially laterally aligned with an exposed portion of the active surface of at least another semiconductor die attached to another, superimposed interposer substrate, the height of the gap between the two interposer substrates being least twice the height of the wire bond loops. In another embodiment of the present invention, an exposed portion of the active surface of at least one semiconductor die attached to an interposer substrate substantially directly faces but is at least partially laterally offset from an exposed portion of the active surface of at least another, opposingly oriented semiconductor die attached to another interposer substrate, the height of the gap between the interposer substrates in this instance being at least one wire bond loop height but less than two. In still another embodiment of the present invention, an exposed portion of the active surface of at least one semiconductor die attached to an interposer substrate substantially directly faces an exposed portion of the active surface of another semiconductor die attached to another interposer substrate but is completely laterally offset therefrom, the height of the gap between the interposer substrates being at least the wire bond loop height. Thus, wire bond height may be minimized, depending upon the opening alignment technique selected. In all of the embodiments, a flowable dielectric material may be disposed within the gap to substantially encapsulate both the wire bonds electrically connecting the opposing die and substrates and the discrete conductive elements connecting the terminals of the second sets on the two interposer substrates. Further, a flowable dielectric material may be introduced between the lowermost interposer substrate of an assembly and a carrier substrate to substantially encapsulate the second plurality of conductive elements.